1. Field of the Invention
This invention relates to a liquid crystal display, and more particularly, to a thin film transistor substrate for a display device and a fabricating method thereof.
2. Description of the Related Art
Generally, a liquid crystal display (LCD) controls light transmittance of liquid crystal material using an electric field, thereby displaying a picture. To this end, the LCD includes a liquid crystal display panel having liquid crystal cells arranged in a matrix, and a driving circuit for driving the liquid crystal display panel. The liquid crystal display panel includes a thin film transistor substrate and a color filter substrate opposed to each other, liquid crystal injected between two substrates, and a spacer to maintain a cell gap between two substrates.
The thin film transistor substrate includes gate lines, data lines, thin film transistors formed as switching devices for each intersection between the gate lines and the data lines, pixel electrodes formed for each liquid crystal cell and connected to the thin film transistor, and alignment films coated thereon. The gate lines and the data lines receive signals from the driving circuits via each pad portion. The thin film transistor applies a pixel signal fed to the data line to the pixel electrode in response to a scanning signal fed to the gate line.
The color filter substrate includes color filters formed for each liquid crystal cell, black matrices for dividing color filters and reflecting an external light, common electrodes for commonly applying reference voltages to the liquid crystal cells, and an alignment film coated thereon. The liquid crystal display panel is completed by preparing the thin film array substrate and the color filter substrate individually to join them and then injecting liquid crystal between them and sealing it.
In such a liquid crystal display, the thin film transistor substrate has a complicated fabrication process leading to a significant increase in manufacturing costs of the liquid crystal display panel because it involves a semiconductor process needing a plurality of mask processes. To solve this, the thin film transistor substrate has been developed toward a reduction in the number of mask processes. This is because one mask process includes a lot of processes such as thin film deposition, cleaning, photolithography, etching, photo-resist stripping and inspection processes, etc. Recently, there has been highlighted a four-round mask process excluding one mask process from the existent five-round mask process that was a standard mask process of the thin film transistor.
FIG. 1 is a plan view illustrating a thin film transistor substrate adopting a four-round mask process, and FIG. 2 is a cross-sectional view of the thin film transistor substrate taken along line I–I′ of FIG. 1.
Referring to FIGS. 1 and 2, the thin film transistor substrate includes a gate line 2 and a data line 4 provided on a lower substrate 42 intersecting with each other and having a gate insulating film 44 therebetween, a thin film transistor 6 provided at each intersection, and a pixel electrode 18 provided at a cell area having a crossing structure. The thin film transistor substrate further includes a storage capacitor 20 provided at an overlap portion between the pixel electrode 18 and the pre-stage gate line 2, a gate pad portion 26 connected to the gate line 2, and a data pad portion 34 connected to the data line 4.
The thin film transistor 6 allows a pixel signal applied to the data line 4 to be charged into the pixel electrode 18 and kept in response to a scanning signal applied to the gate line 2. To this end, the thin film transistor 6 includes a gate electrode 8 connected to the gate line 2, a source electrode 10 connected to the data line 4, a drain electrode 12 connected to the pixel electrode 18, and an active layer 14 overlapping the gate electrode 8 and defining a channel portion between the source electrode 10 and the drain electrode 12. Here, the active layer 14 overlaps the source electrode 10 and the drain electrode 12 to define the channel portion between the source electrode 10 and the drain electrode 12. The active layer 14 also overlaps the data line 4, a lower data pad electrode 36 and a upper storage electrode 22. On the active layer 14, an ohmic contact layer 48 for making an ohmic contact with the data line 4, the source electrode 10, the drain electrode 12, the lower data pad electrode 36, and the upper storage electrode 22 is further provided.
The pixel electrode 18 is connected, via a first contact hole 16 passing through a protective film 50, to the drain electrode 12 of the thin film transistor 6. The pixel electrode 18 generates a potential difference with respect to a common electrode provided at an upper substrate (not shown) by the charged pixel signal. This potential difference rotates a liquid crystal positioned between the thin film transistor substrate and the upper substrate owing to a dielectric anisotropy and transmits a light input, via the pixel electrode 18, from a light source (not shown) toward the upper substrate.
The storage capacitor 20 includes a pre-stage gate line 2, a upper storage electrode 22 overlapping the gate line 2 having the gate insulating film 44 wherebetween, the active layer 14 and the ohmic contact layer 48 therebetween, and the pixel electrode 18 overlapping the upper storage electrode 22 having the protective film 50 therebetween and connected via a second contact hole 24 defined at the protective film 50. The storage capacitor 20 allows a pixel signal charged in the pixel electrode 18 to be stably maintained until the next pixel voltage is charged.
The gate line 2 is connected, via the gate pad portion 26, to a gate driver (not shown). The gate pad portion 26 includes a lower gate pad electrode 28 extended from the gate line 2, and an upper gate pad electrode 32 connected, via a third contact hole 30 passing through the gate insulating film 44 and the protective film 50, to the lower gate pad electrode 28. The data line 4 is connected, via the data pad portion 34, to the data driver (not shown). The data pad portion 34 consists of a lower data pad electrode 36 extended from the data line 4, and an upper data pad electrode 40 connected, via a fourth contact hole 38 passing through the protective film 50, to the lower data pad electrode 36.
Hereinafter, a method of fabricating the thin film transistor substrate having the above-mentioned structure adopting the four-round mask process will be described in detail with reference to FIGS. 3A to 3D.
Referring to FIG. 3A, gate metal patterns including the gate line 2, the gate electrode 8 and the lower gate pad electrode 28 are formed on the lower substrate 42 by a first mask process. More specifically, a gate metal layer is formed on the lower substrate 42 by a deposition technique such as sputtering. Then, the gate metal layer is patterned by photolithography and etching processes using a first mask, thereby forming gate metal patterns including the gate line 2, the gate electrode 8 and the lower gate pad electrode 28. The gate metal layer has a single-layer or double-layer structure of chrome (Cr), molybdenum (Mo) or an aluminum group metal, etc.
Referring to FIG. 3B, the gate insulating film 44 is coated onto the lower substrate 42 provided with the gate metal patterns. Further, a semiconductor pattern including the active layer 48 and the ohmic contact layer 48 and source/drain metal patterns including the data line 4, the source electrode 10, the drain electrode 12, the lower data pad electrode 36 and the upper storage electrode 22 are provided on the gate insulating film 44 by a second mask process.
More specifically, the gate insulating film 44, an amorphous silicon layer, an n+ amorphous silicon layer and a source/drain metal layer are sequentially provided on the lower substrate 42 provided with the gate metal patterns by deposition techniques such as plasma enhanced chemical vapor deposition (PECVD) and sputtering, etc. Herein, the gate insulating film 44 is formed from an inorganic insulating material such as silicon nitride (SiNx) or silicon oxide (SiOx). The source/drain metal is selected from molybdenum (Mo), titanium (Ti), tantalum (Ta) or a molybdenum alloy, etc.
Then, a photo-resist pattern is formed on the source/drain metal layer by photolithography using a second mask. In this case, a diffractive exposure mask having a diffractive exposing portion at a channel portion of the thin film transistor is used as a second mask, thereby allowing a photo-resist pattern of the channel portion to have a lower height than other source/drain pattern portion. Subsequently, the source/drain metal layer is patterned by a wet etching process using the photo-resist pattern to provide the source/drain metal patterns including the data line 4, the source electrode 10, the drain electrode 12 being integral to the source electrode 10 and the upper storage electrode 22. Next, the n+ amorphous silicon layer and the amorphous silicon layer are patterned at the same time by a dry etching process using the same photo-resist pattern to provide the ohmic contact layer 48 and the active layer 14.
The photo-resist pattern having a relatively low height is removed from the channel portion by the ashing process and thereafter the source/drain metal pattern and the ohmic contact layer 48 of the channel portion are etched by the dry etching process. Thus, the active layer 14 of the channel portion is exposed to disconnect the source electrode 10 from the drain electrode 12. Then, the photo-resist pattern left on the source/drain metal pattern group is removed by a stripping process.
Referring to FIG. 3C, the protective film 50 including the first to fourth contact holes 16, 24, 30 and 38 are formed on the gate insulating film 44 provided with the source/drain metal patterns. More specifically, the protective film 50 is entirely formed on the gate insulating film 44 provided with the source/drain metal patterns by a deposition technique such as plasma enhanced chemical vapor deposition (PECVD). Then, the protective film 50 is patterned by photolithography and etching processes using a third mask to thereby define the first to fourth contact holes 16, 24, 30 and 38. The first contact hole 16 is formed through the protective film 50 to expose the drain electrode 12, whereas the second contact hole 24 is formed through the protective film 50 to expose the upper storage electrode 22. The third contact hole 30 is formed through the protective film 50 and the gate insulating film 44 to expose the lower gate pad electrode 28. The fourth contact hole 38 is formed through the protective film 50 to expose the upper data pad electrode 36. The protective film 50 is made from an inorganic insulating material identical to that of the gate insulating film 44, or an organic insulating material such as an acrylic organic compound having a small dielectric constant, BCB (benzocyclobutene) or PFCB (perfluorocyclobutane), etc.
Referring to FIG. 3D, transparent conductive film patterns including the pixel electrode 18, the upper gate pad electrode 32 and the upper data pad electrode 40 are provided on the protective film 50 by a fourth mask process. A transparent conductive film is entirely deposited onto the protective film 50 by a deposition technique such as sputtering. Then, the transparent conductive film is patterned by photolithography and etching processes using a fourth mask to provide the transparent conductive film patterns including the pixel electrode 18, the upper gate pad electrode 32, and the upper data pad electrode 40. The pixel electrode 18 is electrically connected, via the first contact hole 16, to the drain electrode 12 while being electrically connected, via the second contact hole 24, to the upper storage electrode 22 overlapping with the pre-stage gate line 2. The upper gate pad electrode 32 is electrically connected, via the third contact hole 30, to the lower gate pad electrode 28. The upper data pad electrode 40 is electrically connected, via the fourth contact hole 38, to the lower data pad electrode 36. Herein, the transparent conductive film is formed from indium-tin-oxide (ITO), tin-oxide (TO) or indium-zinc-oxide (IZO).
As described above, the related art thin film transistor substrate and the fabricating method thereof as mentioned above adopts the four-round mask process, thereby simplifying the process and reducing manufacturing costs. However, because the semiconductor layer and the source/drain metal layer are patterned by a diffractive exposure mask process, the semiconductor layer remains at an unnecessary portion.
For instance, as shown in FIG. 2, the semiconductor layer including the active layer 14 and the ohmic contact layer 48 remains under the upper storage electrode 22 of the storage capacitor 20. As a result of the remaining semiconductor layer, a distance between the upper storage electrode 22 and the gate line 2 that is a lower storage electrode is far away, thereby reducing a capacitance value of the storage capacitor 20 in an inverse proportional with the distance. For this reason, the storage capacitor 20 fails to stably keep a pixel signal charged in the pixel electrode 18.